Cascade multiplier



y 6, 1969 A. NATHAN 3,443,079-

CASCADE MULTIPLIER Filed Sept. 12, 1963 -Sheet 1 of5 FIGJ B INVENTOR y 6,1969 A. NATHAN 3,443 1 CASCADE MULTIPLIER Filed Sepf. 12. 1963 Sheet 2 015 INVENTOR y 6, 1969 'A. NATHAN 3,443,079

CASCADE MULTIPLIER I Fil ed Sept. 12. 1963 Sheet 3 of 5 FIG. [0

INVENTOR 84 v Sheet Filed Sept. 12. 1963 INVENTOR y 6, 1969- I A. NATHAN 3,443,079

CASCADE MULTIPLIER Filed Sept. 12. 1963 Sheet 5 of5 1N VENTOR United States PatentO 3,443,079 CASCADE MULTIPLIER Amos Nathan, Dept. of Electrical Engineering, Techilion, Israel Institute of Technology, Haifa, Israe Filed Sept. 12, 1963, Ser. No. 308,462 Int. Cl. G06g 7/16, 7/12 US. Cl. 235194 15 Claims This invention relates to multipliers wherein an output signal is produced from two input signals, corresponding to the value of their product. More specifically, this invention provides multipliers wherein a plurality of signals is produced which are combined in a linear manner and yield an output signal approximating said product. Multipliers according to the invention include a plurality of cascade connected stages. The first stage is a converting stage; the second stage is either a converting stage or a multiplier.

A converting stage produces a converted output signal such that (1) it is a piecewise-linear function of the input signals; (2) a linear function thereof is a first approximation of the required product, and the error of approximation is itself the product of linear functions of converted signals.

Conversion is to be understood in the sense of US. Patent No. 801,469 and Amos Nathan, Input Converters for Generators of Symmetric Functions, The Institution of Electrical Engineers (London), Monograph No. 522E, June 1962.

Because of property (1), converted signals can be produced with great accuracy. Because of (2) (a) one or more converting stages can by connected in cascade; (b) the accuracy increases, in general, with the number of converting stages used; (c) in a cascade multiplier of given accuracy, it is possible to use a multiplier of lower accuracy.

It is an object of the invention to provide multipliers producing an output signal as the sum of two or more signals, wherein at least one of said signals is a piecewiselinear function of the input signals.

It is a further object of the invention to provide means for the conversion of multipliers of given accuracy into multipliers of higher accuracy.

It is a yet further object of the invention to provide analog multipliers for the production of an output voltage representing the product of the instantaneous values of two input voltages.

A still further object of the invention is the provision of iterative analog or digital multipliers, wherein one converting stage is used two or more times in succession.

Further objects and advantages of the invention will become apparent from the following description taken in connection with the appended drawings, in which:

FIGURE 1 is a plot of the plane of variables;

FIGURES 2 to 6 are diagrams of converting circuits A, B, C, D, A", which may be used in embodiments of the invention;

FIGURE 7 is a schematic diagram of one embodiment of the invention;

FIGURE 8 relates to another embodiment of the invention;

FIGURE 9 is a schematic diagram of a further embodiment of the invention;

FIGURES 10 and 11 relate to iterative analog embodiments of the invention;

FIGURE 12 plots the switching sequence of the example of FIGURE 10;

FIGURE 13 is a plot of an auxiliary voltage for FIG- URE 10;

FIGURES 14 to 16 are flow diagrams relating to digital embodiments of the invention.

Consider the function where M is an arbitrary positive constant, variables x and y are in domain HFBG, FIGURE 1, where 0G=0B=0F=OH=M, and O is the origin of the x,y co-ordinate system. Therefore, M x,y M and z assumes its maximum value at x=y=M/2 and its minimum value at x: y=M/ 2. Thus u and v can be determined from equivalent expressions, for example from The transformation (12 v '=v M/2 defines a u v system of co-ordinates whose origin is at O, the center of OABC. a v are restricted to region OABC.

From Equations 3 and 12,

and the range of 2 is one quarter of the range of 2. By Equations 13 and 16, V214 is a first approximation to z and z, is the error term.

If 2 is computed by Equation 13 and 2 has a fractional error e with respect to its range, the fractional error caused in z is only A)e.

2 Equation 14, can be expressed in a similar manner, defining in analogy with Equations 4 and 5 and in analogy with equation 12) where M/4 is the signal shift which is equal to /2O'B, FIGURE 1. It follows from Equation 14 that and from Equation 13 1+( )"2+ a' z, is maximum at u =v /z (M/4) =M/ 8 and minimum at u =v '=M/ 8, and therefore (24) -M/64= M/4 z M/ 4 =M/ 64 In general, defining 2 can be written, when x and y are in HFBG, FIGURE 1,

so that, by Equation 2, the range of 2,, is A times the range of z. 2 Equation 28, is therefore an approximation to z to within a maximum fractional error of or, equivalently, a maximum absolute error iM/4 which should be compared with z =M/4.

The invention provides implementations of multipliers corresponding with Equation 28 or 29 in order to produce a product function.

FIGURES 2, 3, 4, and 5 are schematic diagrams of converting circuits A, B, C, and D for the production of voltages u,, u,, v,, and --v according to Equations 4, 6, 5, and 7, respectively, from input voltages x and y and their inverses. In these examples diodes I serve as selecting elements. In the circuit of FIGURE 2, for example, the smaller of x and y is selected at terminal 2 and the smaller of x and --y is selected at terminal 4; subsequently the larger of the signals so selected is selected at terminal 3 where voltage u, is thus produced. Voltage -x and y can be produced from x and y with the help of sign changers of unity gain.

FIGURE 6 is a schematic diagram of an example of a converter producing voltage u, according to Equation 8. The input voltages are x and y. The smaller of x and -y is selected at terminal 4' by first selecting the larger of x and y at terminal 4 and subsequently changing its sign in sign changer 31'.

FIGURE 7 is a schematic diagram of one embodiment of a multiplier according to the invention corresponding to Equation 23. 5, 6, 7, and 8 are input converters A, B, C, D producing at terminals 9, 10, 11, 12 voltages 14,, -u;, v ---v respectively. The shifted voltage v, is produced at terminal 17 by deducting from v at terminal 11 the voltage drop produced in resistor 13 by a constant current i which is withdrawn from terminal 17 by current generator 15. Terminal 17 is not loaded so that all the current i flows through resistor 13. Voltage v, is similarly produced at terminal 18 by adding to v, at terminal 12 the voltage rise in resistor 14 caused by current i which is supplied to terminal 18. In this example, M=100 volts, and, by Equations 1 and 12, z=(1/100)xy volts,

V1=V150 volts. 19 are impedance converters which transfer voltages 11,, u,, v,', and v;' to lines 20, 21, 22, and 23, respectively, at a low impedance level, without substantially loading their input terminals.

A second converting stage is connected in cascade with the first stage and produces a second set of converted voltages u u v ',v at terminals 9', 10', 11', 12', respectively, in a similar second stage, from +u u +v and v, as input voltages according to Equations 17 and 18, and, by Equation 19, v '=v 25 volts and -v;,' at terminals 17 and 18', respectively. The required shifts are produced in resistors 13 and 14'. The voltages at terminals 9', 10', 17', 18' are transferred to lines 24, 25, 26, 27, respectively, through impedance converters.

Multiplier 28 is connected in cascade with the second stage and produces voltage Z at terminal 29 from voltages u -u v v,, as input voltages. Sign changing adder 31, having gain A, produces an output voltage equal to Az at terminal 33. At terminal 32 a constant voltage can be added to the output voltage. Only ,6 of any fractional error of multiplier 28 is contributed to the error of multiplication at output terminal 33.

FIGURE 8 is a schematic diagram of one stage of another embodiment of a multiplier according to the invention, producing voltages 214 and 2v Voltages a and v, are produced from voltages x, x, y, and y in converters A and C, shown at 5 and 7. 40 is a sign changer of gain -2 and produces from u, voltage 2u at line 46. 41 is a unity gain sign changer producing from Zu, voltage 21:, at line 47. 43 is a sign changing adder of gain -2 producing voltage 2v at line 48 from voltage --V2M at terminal 42 and from v 45 is a unity gain sign changing adder producing from 2v voltage 2v, at line 49. If 2a,, -2u 2v 2v replace x, x, y, y. respectively, as input voltages, there are produced at lines 46, 47, 48, 49 voltages 4u 4u 4v 4v respectively. Therefore, connecting in cascade n stages, there are produced voltages 211 411 2 a,, and z Equation 29, follows by addition from n= 1)+%e( z)+ n) A time sharing embodiment of the invention need use only one device corresponding to FIGURE 8. Voltages 2a,, 4a,, 2%,, are produced in succession at line 46. For this purpose, voltage 211, is stored in store S, say, and voltages 2a, and 2v are stored in store T. Voltages -2u and 2v are produced. 214,, --2u 2v --2v,' are subsequently used as input signals instead of x, x, y, y, respectively, thereby producing 411 4u 4V2, 4v on lines 47, 46, 49, 48, respectively. (M0411 is added to voltage 214; in store S. 4u and 4v next replace 211, and 2v respectively, in store T, and the cycle is repeated. After n cycles the signal in store S is 42,,- This signal is transferred to an output store. Next store T is cleared and new values x, x, y, y are used as input signals, and the process is continued. It is evidently possible to use this system in order to provide the product of two or more pairs of variables. For this purpose, as in any time-sharing system, the device is used successively to provide the required products, by means of suitable input and output switching. A plurality of stores s is required for the purpose, one each for each required product, but only one device corresponding to FIGURE 8 is required.

Alternatively, in FIGURE 8, adders 40 and 43 have a gain -1 and the circuit produces n u,, v --v, at lines 47, 46, 49, 48, when x, x, y, --y are the input voltages. If these are replaced by u, u, v, -v, respectively, and the voltage at terminal 42 is made equal to M/2 the circuit produces voltages 11 u,, v,, v,'.

A still further embodiment of the invention will be described in connection with FIGURE 9. Voltages u, and v, are produced on lines 46 and 48, respectively, as before. Converter A, 50, produces therefrom at line 51 signal u; and sign changing adder 53 produces at terminal 54 the voltage z /2u +%.u which is an approximation to z having a maximum fractional error of A can be implemented, for example, in correspondence with Equation 9, according to in a circuit corresponding with that of FIGURE 6 but having diodes and voltage sources of reversed polarity.

FIGURE 10 is a schematic diagram of an example of a repetitive embodiment of the invention, in which one converting stage is used on a time sharing basis. In this example, there are 6 time intervals to a computing cycle. Converters A and C produce at lines 73 and 74 voltages a and v respectively, from input voltages x, x, y, and y at lines 69, 70, 71, 72, respectively, during the first computing interval, and /2u /zv /2u and /zv are produced therefrom. During the second interval, /zu /zu -v /2v replace x, -x, y, y at lines 69, 70, 71, 72, respectively, causing the production of Au, and /zv at lines 73 and 74, respectively. In a similar manner (M011 and A)v are produced in the third interval and (%)u., and /s)v in the fourth interval. The voltage kz where k is a constant of proportionality and 2 is given by is produced at output terminal 78 from 2( /z )u i=1, 2 4; at terminal 73.

Switching, storage, transfer and output production are performed in the example in circuits including integrating circuits 61-66. Integrators 61 and 63 can be in one of three states, H, R and S; integrators 62, 64 and 66 can be in the two states H and R; integrators 65 can be in three states, H, R and I; according to the position of their associated change-over elements, such as 58 in integrator 61. Except for integrator 65, these units are not used as integrators proper, but rather for signal storage and transfer, and the term integrator derives from the circuit configuration. The sequence of positions of the changeover elements during one cycle is shown in FIGURE 12. Curve I applies to integrators 61 and 63; curve 11 to integrators 62 and 64; curve III to integrator 65; curve IV to integrator 66. Curve II further applies to changeover switches 67 and 68. The voltage at terminal 69 is switched in accordance with the curve shown in FIG- URE 13.

The letters H, R and S denote hold, reset and start, and the letter I denotes integrate.

Voltage x is received by integrator 61 at terminal 56. During the first interval this integrator is in state S and voltage -x is produced at terminal 59 and transferred through switch 67, in state R, to line 70'. Unity gain sign changer 79 produces from --x the voltage x on line 69. Integrator 63 receives at terminal 57 voltage y and similarly produces y and y at lines 71, 72, respectively. Converters A and C thus produce on lines 73- and 74 voltages u, and v respectively.

Integrator 65 receives voltage u, at line 73 during the first interval. Integrators 62 and 64 are in their R position and produce at their output terminals 75, 76 voltages /2u and -%v respectively. Integrator 62 functions as a sign changer of gain /2, While in position R, while integrator 64 functions as a sign changing adder, receiving voltage E on line 55 and voltage V, on line 74 and producing therefrom voltage /2v During the second interval, voltage /2u at terminal 75 is held by integrator 62, now in the hold position, /2u is transferred through switch 67 to line 70 and voltage /2u is produced therefrom in sign changer 79 at line 69. Similarly, voltages /2v and /2v are produced on lines 71 and 72, respectively. Converters A and C thus produce at lines 73 and 74 voltages V214 and /zv respectively. Integrator 61, now in the reset position, produces (%)u at terminal 59 and integrator 63 produces A)v at terminal 60 frorn /z v at line 74 and the new voltage A )E at terminal 55. Integrator 65 receives voltage u during this second interval. Similar third and fourth intervals follow, and the voltages at line 73 are (%)u in the third and (%)u, in the fourth interval. In the fifth interval integrator 65 is in the hold position. The voltage produced at output terminal 77 of integrator 65 at the end of the fourth interval is proportional to -z as required. This voltage is held during the fifth interval. Integrator 66, in the reset position during this interval, functions as a sign changer and thus produces a voltage proportional to (-z;) :2, at its output terminal 78.

During the sixth interval, integrator 65 is in the reset position and produces voltage zero at terminal 77 and integrator 66 is in the hold position, which it maintains during the next five intervals, thus holding a constant output voltage. The seventh interval is identical with the first and a new cycle begins, operating upon new values x and y.

The device can be used in an evident manner to produce the products of two or more pairs of voltages x and y. For each pair a separate integrator 66 is required and switching proceeds in successive computing cycles in order to receive the associated x, y pairs and to feed the result of computation into the associated integrator 66.

FIGURE 11 shows the switching of input voltages and of holding integrators 66 required if three pairs of products, x y x y x 3 are to be produced in the circuit of FIGURE 10. The three holding integrators 66, 80, 81 replace 66. Output terminal 78 is replaced by terminals 82, 83, 84. 56 and 57 are the x and y input terminals of integrators 61 and 63, respectively, and 77 is the output terminal of integrator 65, FIGURE 10. Switching occurs once every computing cycle. Thus any input voltage is received during one cycle and skipped during the following two cycles.

An alternative way of carrying out the invention applies the same voltage E at terminal 55, FIGURE 10, throughout all intervals and uses intervals of varying duration. The second, third and fourth intervals being A., ,6 times the first interval, respectively. Integrators 61-64 have four times the gain described above, when in position R, so that, for example, -2u is produced at terminal 75 from ti at terminal 73, during the first interval. The duration of the fifth and sixth intervals is of no consequence. The sequence of voltages thus produced at line 73 is 11 214 4u 8a,. Integrator 65 produces therefrom at the end of the fourth interval a voltage proportional to In fast embodiments of the invention electronic switches are used in order to perform all the switching operations.

It is by no means an essential feature of the invention that variables be represented as continuously variable voltages. Analog embodiments of the invention can use representation of variables in the form of currents or as mechanical quantities, for example. Any representation permitting the operations of maximum and/or minimum selection, signal shift and change of sign as well as addition can be used in order to carry out the invention. Moreover, variables need not even be represented in analog form, but may be represented in digital form as will now be described in detail by way of example.

Digital devices for the performance of storage, signal shift, change of sign, selection and addition are of the prior art. FIGURE 14 is a flow diagram showing the organization of a binary multiplier according to the invention. The value of the quantity M as defined in connection with FIGURE 1 is taken as 2 and x and y are limited to 1 x, y 1, which ensures that x, y is in domain HFBG, FIGURE 1, as required.

Number representation is, for example, in a twos complement manner using m bits, or digits. From x=u and y=v,, received by block there are produced 11 and v requiring the A and C operations defined in Equations 4 and 5, respectively. Block 91' receives v and produces therefrom v as defined in Equation 12, where M=2, i.e. v =v l. Block 92 receives it, and stores u u and v subsequently replace x and y as inputs to block 90'.

In general, a computing cycle produces from u, and v, in block 90' the numbers u and n and in block 91' from v the number v '=v, /2 and adds A. 'z1 to the number stored in block 92'. Multiplication by /5. and its powers is accomplished by a shift,

7 one place to the right for each power, i.e. i+1 places to the right for /z) An example of carrying out the invention according to the scheme of FIGURE 14 will be described in greater detail in connection with the diagram of FIGURE 15. It follows from Equations 25-27, with M=2 that Moreover, for u, there is the alternative (a) if the signs of u; andv, are equal then (b) if the signs of u; and v, are opposite then The system must produce u and VH1 from u, and v Blocks 90 and 91 accept it, and v and produce -u; and --v respectively, by sign changing. Block 90 fu ther selects the positive of u, and u,, i.e. [u,[=e, and produces it as 92 and the negative, -]u,[=c and produces it at 93. Block 91 simultaneously produces [v,'l=f at 94 and ]v '|=d at 95. 96 and 97 produce from e and f the quantity a=lu l( /z) and the quantity b=|v /2) respectively.

Block 98 compares lu l with |v and activates line 100 if |rq| lvf| and line 101 otherwise, selecting the quantity a in 96 if lu lzlv 'l and the quantity b in 97 if |u l [v /2. The selected quantity is n Block 99 compares the signs of u, and v, and activates line 102 if the signs are equal and line 103 otherwise. Blocks 104-107 determine which of the quantities c, d, e and f equals u in accordance with cases (a) and (b) above. For example, if line 102 is activated, i.e. case (a) applies, and simultaneously |u |v so that line 101 is activated, only at 106 are both incoming lines activated and this block carries out selection; it selects the quantity e=lu l in accordance with Equation 34. The three other cases are dealt with in an analogous manner. a; and v, are next replaced by u and n which are now known. The process is initiated with x=u and y=v and carried on a sufficient number of times in order to give the required product xy with sufficient accuracy.

FIGURE 16 is a block diagram of a digital embodi ment of the invention that is a variation of the embodiment corresponding to FIGURE 15. Blocks 110 and 111 receive a, and v respectively, as before, but now also their inverses are so received. Block 110 produces signals e and -e on different lines, and no sign changing is required for the purpose. Block 111 similarly produces f and d. Blocks 96 and 97 produce a and b as before, and blocks 96' and 97' simultaneously produce a and b from c=e and d=f, respectively, according to the relations Blocks 98 and 99 function as before. The n selectors are blocks 112 and 113 which select in this embodiment both V and v respectively, in accordance with the symbols written in the left and right part thereof, respectively. Thus, if line 100 is activated, for example, block 112 is active and selects a and -a as n and -v respectively. Blocks 114-117 are the u selectors, selecting both u and u in accordance with the symbols in the left and right parts thereof, respectively. Thus, if lines 101 and 102 are activated, block 115 is active and e and c are selected as u, and u respectively. In the next cycle, u u, v v replace 11 u,, v,', v{, respectively, as input quantities. The first cycle begins with x=u -x=u y=v 0'- The number n of required computing cycles to give z with a given accuracy, follows from Equation 31, with M=2, recalling that 2,, is the error term. The term cycle as used above in connection with the description of digital embodiments of the invention corresponds to the term interval in the description of repetitive analog embodiments of the invention.

Although this invention has been described and illustrated in detail it is to be clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation.

What I claim is:

1. A cascade multiplier for the production of an output quantity representing the product of first and second variables, comprising first and second means for receiving first and second input quantities representing said variables, respectively; a first stage connected thereto for producing by a process of selection of maximum and minimum of said quantities and their inverses, first and second converted quatities, wherein said first converted quantity corresponds with a first approximation of said output quantity; means adapted to effect a predetermined shift of said second converted quantity to produce a third converted quantity; generating means responsive to said first and third converted quantities for producing therefrom at least one further quantity such that a linear function thereof and of said first converted quantity corresponds with an improved approximation of said output quantity; and linear combining means arranged to receive said first converted quantity and said further quantity for producing said output quantity.

2. The multiplier as claimed in claim 1, wherein a linear function of said first converted quantity and the product of said first and third converted quantities represents said output quantity.

3. The multiplier as claimed in claim 2 wherein said first stage is adapted to produce said first converted quantity by a process of selection of one of (1) one of said first and second input quantities having a predetermined magnitude relation with respect thereto and (2) one of the inverse of said first and the inverse of said second input quantities having a predetermined magnitude relation with respect thereto; and to produce said second converted quantity by a process of selection of one of said first and second input quantities and their inverses having a predetermined magnitude relation with respect thereto.

4. The multiplier as claimed in claim 3, wherein said generating means includes means for producing a further converted quantity corresponding with the greater of (1) the smaller of said first and the third converted quantities and (2) the smaller of their inverses, said further converted quantity representing said further quantity.

5. A cascade multiplier for the production of an output quantity representing the product of first and second variables, comprising first and second means for receiving first and second input quantities representing said variables, respectively; a first stage connected thereto and having said quantities as first and second input quantities, respectively; and including n+1 stages, the (i+1)th thereof connected to the ith thereof; where n is a positive integer and i=1,2 n; wherein the ith stage is adapted to produce associated first, second and third converted quantities; the (i+1)th stage having said ith first and third converted quantities as first and second input quantities, respectively; each of said plural stages including first means for producing said associated first converted quantity by a process of selection of one of (1) one of its said input quantities having a predetermined magnitude relation with respect thereto and (2) one of the inverse of its said input quantities having a predetermined magnitude relation with respect thereto; said stage including second means for producing said associated second quantity by a process of selection of one of its input quantities and their inverses having a predetermined magnitude relation with respect thereto, and means to effect a shift of said second converted quantity to produce said associated third converted quantity; said cascade multiplier including combining means arranged to receive said plural first converted quantities for producing said output quantity; and wherein said first converted quantity associated with said first stage corresponds with a first approximation of said output quantity and a linear function of said first converted quantities associated with said first and second stages corresponds with an improved approximation of said output quantity.

6. A time sharing multiplier comprising the device as claimed in claim 5, wherein said generating means includes means for storing said first converted quantity and at least one of said second and third converted quantities; means for replacing said first and second input quantities by said first and third converted quantities to cause the production in said first stage of a second pair of converted quantities, during a second computing interval; means adapted to cause the repetition of the process of production of converted quantities in said first stage n+1 times, where n is a positive integer; said combining means arranged to receive said plural first converted quantities.

7. An analog cascade multiplier comprising the device as claimed in claim 1, wherein said quantities are represented by the values of corresponding analog signals.

8. The device as claimed in claim 7, wherein said analog signals are in the form of electric potentials.

9. The multiplier as claimed in claim 8 and including resistive means connected in the signal path arranged to be traversed by a predetermined current to cause a predetermined potential diiference therein for producing said shift of said second converted quantity.

10. The device as claimed in claim 8 wherein said first stage includes a plurality of diode means responsive to selected ones of said first and second input quantities and their inverses, said diode means having a common output connection for the production of said second converted quantity thereat.

11. An analog cascade multiplier comprising the device as claimed in claim 5, wherein said quantities are represented by the values of corresponding analog signals.

12. An analog cascade multiplier comprising the device as recited in claim 5 and including multiplier means connected to said (n+1)th stage for producing a product quantity corresponding with the product of said first and third converted quantities associated therewith; said combining means being arranged to receive said product quantity.

13. The device as claimed in claim 7 wherein said generating means includes multiplier means for the production of said further quantity.

14. The multiplier as claimed in claim 6, wherein said quantities are represented by the values of corresponding analog signals.

15. The multiplier as claimed in claim 14, wherein said repeated process is arranged to include a sequence of intervals of decreasing duration.

No references cited.

MALCOLM A. MORRISON, Primary Examiner. I. F. RUGGIERO, Assistant Examiner.

US. Cl. X.R. 3 07-229 UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTIQN Patent No. 3,443,079 May 6, 1969 Amos Nathan It is certified that error appears in the above identified patent and that said Letters Patent are hereby corrected as shown below:

Column 2, line 62, "M/ should read M/4, Column 3, line 53, "5, 6, 7, and 8" should read 5 6 Z, and 8 line 72, "v2" should read v Column 4, line 1, "17" should read 17 line 50, "5" should read S Column 8, line 18, "quatities" should read quantities Signed and sealed this 21st day of April 1970.

(SEAL) Attest:

WILLIAM E. SCHUYLER, JR.

Commissioner of Patents Edward M. Fletcher, Jr.

Attesting Officer 

1. A CASCADE MULTIPLIER FOR THE PRODUCTION OF AN OUTPUT QUALITY REPRESENTING THE PRODUCT OF FIRST AND SECOND VARIABLES, COMPRISING FIRST AND SECOND MEANS FOR RECEIVING FIRST AND SECOND INPUT QUANTITIES REPRESENTING SAID VARIABLES, RESPECTIELY; A FIRST STAGE CONNECTED THERETO FOR PRODUCING BY A PROCESS OF SELECTION OF MAXIMUM AND MINIMUM OF SAID QUANTITIES AND THEIR INVERSES, FIRST AND SECOND CONVERTED QUANTITIES, WHEREIN SAID FIRST CONVERTED QUANTITY CORRESPONDS WITH A FIRST APPROXIMATION OF SAID OUTPUT QUANTITY; MEANS ADAPTED TO EFFECT A PREDETERMINED SHIFT OF SAID SECOND CONVERTED QUANTITY TO PRODUCE A THIRD CON- 